The present invention relates to a semiconductor device and a method of manufacturing the semiconductor device and, more particularly, to a semiconductor device in which the short channel effect of a MOS transistor is suppressed and a method of manufacturing the semiconductor device.
Recently, in the important potions of computers or communication equipments, large-scale integrated circuits (LSI) each constituted in such a manner that a large number of transistors, resistors, etc. are connected together so as to constitute an electric circuit and thus integrated on one chip are used in many cases.
Due to this, the performance of an equipment as a whole is deeply connected to the performance of the LSI itself. The enhancement in performance of the LSI itself can be realized by minute-structuring the elements. For example, in case of a MOS transistor, by reducing the size thereof, the increase in speed thereof, the reduction in power consumption thereof, and the enhancement in the degree of integration thereof could so far be realized.
However, various problems are caused as a result of the reduction in size of the elements. For example, the shortening of the channel length achieves the effect of lowering the channel resistance on the one hand but, on the other, gives rise to the problem that a short-channel effect is brought about.
As for the suppression of this short-channel effect, it is already found that it is effective to reduce the junction depth of the source/drain; particularly in case of a low supply voltage, it is effective to form a shallow diffusion layer with a high impurity atom concentration at a position near the gate electrode. In other word, it is effective to replace, in the LDD structure, its shallow diffused layer with a low impurity atom concentration with a diffused layer with a high impurity atom concentration. This diffused layer with a high impurity atom concentration is ordinarily known as an extension layer. Or, by enhancing the impurity atom concentration in the region immediately beneath the channel region (by forming a punch through prevention layer), the effect of suppressing the punch through phenomenon is obtained.
However, in case of any of the above-mentioned methods, there is encountered the difficulty that, as the element size is reduced (as the degree of structural minuteness of the elements is furthered), the formation of a very sharp profile, that is, the formation of a very shallow extension layer with a high impurity atom concentration, the formation of a punch through prevention layer beneath a very shallow channel region, etc. become harder.
Further, as a result of the reduction in size of the elements, the ratios of the various parasitic components become relatively high. For example, the junction capacitance of the source/drain is brought to so high a ratio as to affect the operating speed.
As a countermeasure to the above-mentioned difficulty, there has been tried the method of removing the junction capacitance in such a manner that, using a very thin SOI (Silicon On Insulator) substrate, the bottom surface of the junction is contacted with the buried oxide film.
However, in case of this method, the price of the SOI substrate is high and thus costs high, and besides, since the element operation region lies on the buried oxide film, the carries produced through the element operation are accumulated. That is, a so-called substrate accumulation effect is caused, and thus, there arises the problem that it becomes difficult to operate the elements stably.
Further, there has also been proposed the technical concept that a back gate is formed in the buried oxide film in a very thin SOI substrate, and, to this back gate, a voltage is applied to render the region beneath the channel into a depleted state and thus to prevent a punch through, whereby the short channel effect can be suppressed.
As described above, in order to suppress the short channel effect of the MOS transistor, the introduction of an extension layer or a punch through prevention layer has been proposed, but there arises the other problem that, as the structural minuteness of the elements is furthered, it becomes hard to suppress the short channel effect of the MOS transistor.